Technology: Rad Hard eFPGA

Delivering radiation-hardened eFPGA IP that meets the most stringent reliability requirements that outperforms TMR and DICE with modest area overhead

The most vulnerable parts of a computer chip to radiation effects are flip-flops. For proton-dominated space environments Chameleon eFPGAs meet or exceed the error-rate of legacy rad-hard FPGAs or solutions based upon triple modular redundancy while shrinking the configuration cell area by roughly an order of magnitude.

Based on a 22nm test chip developed in conjunction with Sandia, at 0.18 × the area of TMR, the Chameleon tile reaches the same "zero visible upsets" level up to at least 4 × 10¹² cm⁻²—equivalent to > 10 krad(Si) TID and > 100 years in LEO behind 5 mm Al shielding

White Papers

Emulation-based Fault Injection
A Radiation Hardened by Design FPGA with Distributed Single Event Upset Sensors, Embedded Error Handler, and 8Mb Embedded MRAM Configuration Storage in 22nm Bulk FinFET CMOS
Design and Evaluation of Flip-Flops for eFPGA Configuration Hardening
A Soft Error Tolerant Flip-Flop for eFPGA Configuration Hardening in 22nm FinFET Process
(more whitepapers coming soon!)