PQC Agility White Paper
Learn how Chameleon eFPGA enables instant algorithm updates—no silicon respin required.
Get White PaperPQC Agility White Paper
Learn how Chameleon eFPGA enables instant algorithm updates—no silicon respin required.
Get White PaperASICS are frozen.
Algorithms, standards, & threats are not.
What Chameleon Delivers
Synthesized, software-defined embedded FPGA tailored to your exact specifications
- RTL-based eFPGA delivers true process node and fab independence
- Best in class power, performance, and area – optimized to your requirements
Avoid obsolescence, eliminate security threats, address changing market standards & requirements
- Extend product life
- Protect high value IP
- Expand served markets
- Support changing workloads
- Low-cost ASIC "insurance"
- Late-stage bug fixes
Highest levels of security
- US based, onshore RTL based eFPGA
- Supports hardware redaction – "hidden in plain sight"
- Supports NIST PQC agility requirements
- No IP leakage
- 100% secure IP delivery – no manual netlist review or intervention required
- Protected configuration bit stream
The Chameleon eFPGA Advantages
Silicon proven technology and design flow
Multiple test chips on multiple fabs and process nodes
Based on industry open-source tool suite
Provides vendor independence - avoids tool and IP obsolescence
Drops into standard design flow
Drops into standard design and verification CAD flow
Chameleon Semiconductor
- Optimized for application
- Can't reverse engineer
- Process node independent
- Supports redaction
- Hidden in plain sight
- Lowest cost solution
Embedded Hard Macro
- Not optimized for application
- Subject to reverse engineering
- Locked to a process node
- Does not support redaction
Chiplet Hard Macro
- Not optimized for application
- Subject to reverse engineering
- Process node independent
- Does not support redaction
- Low yield, complex packaging