Specify your exact eFPGA requirements for your design. Our software automatically generates the synthesizable RTL and configuration bitstream.
Seamlessly integrate into your existing CAD flow with complete control over fabric architecture, resource allocation, and timing constraints.
No black-box license servers, no foundry-lock in, no surprises at tape-out.
Avoids any IP leakage – no need for Chameleon review or sign-off
Built on industry-standard open-source tools including Yosys for synthesis and VPR for place-and-route.
Open-tools ensure transparency while eliminating vendor lock-in and obsolescence.
Define your exact eFPGA architecture. Specify the CLB type (4-input or 6-input LUTs), BRAM and DSP mix, and routing resources—via specification files that drive our automated generation flow.
Our Chisel-based fabric generator constructs the complete RTL implementation, automatically inserting scan chains for testability and manufacturing validation.
VPR-based place-and-route ensures optimal physical implementation, generating configuration bitstreams tuned to your specified fabric topology.
Routing resources are fully customizable and automatically optimized to balance interconnect flexibility against die area constraints.
The result: a bespoke eFPGA fabric precisely matched to your application’s performance, power, and area requirements—generated automatically from architecture to silicon.
Implement your design onto Chameleon eFPGA using an open, automated flow built on industry-standard tools.
Synthesize your RTL into LUT netlists using Yosys, the trusted open-source synthesis suite supporting Verilog and System Verilog inputs.
Our Python parser bridges synthesis output to VPR, automatically converting netlists into the physical representation required for place-and-route on your custom eFPGA fabric.
VPR performs timing-driven placement and routing, optimizing for your specified architecture while generating the configuration bitstream that programs your eFPGA.
Verify functional correctness pre-silicon using Cocotb, the Python-based verification framework enabling rapid testbench development and regression testing of mapped designs against golden references.
The complete flow—from RTL to verified bitstream—integrates seamlessly into your existing CAD environment without proprietary tool dependencies.
Configurable logic blocks arranged in a regular array, interconnected through programmable switch blocks enabling flexible routing topologies.
Each logic block contains LUTs, flip-flops, and arithmetic carry chains for efficient implementation of combinational and sequential functions.
Switch blocks provide programmable connectivity between adjacent logic blocks, supporting nearest-neighbor and longer-distance routing resources optimized for speed or area.
Dedicated I/O blocks (IOBs) interface the eFPGA array to the internal SoC logic.
Each logic block (LB) contains eight, 4-input or 6-input basic logic elements (BLEs), interconnected via an internal crossbar switch for highly flexible routing.
The BLE supports both registered and unregistered outputs, enabling efficient implementation of pipelined or purely combinational functions.
Each LB interfaces to horizontal and vertical routing channels through a programmable connection block, providing access to global interconnect resources.
Switch blocks at routing channel intersections interconnect horizontal and vertical wire segments, creating a scalable, mesh-based routing fabric optimized for timing and routability.
