Technology: Hardware Redaction

The industry’s best in class technologies combined to deliver the industry’s leading eFPGA solution.

Hidden in plain sight

Chameleon eFPGA-based redaction gives IP owners a document-style "black-bar" capability for hardware: critical pieces are simply missing from the delivered gate-level description, yet can be re-instated in the field, delivering strong reverse-engineering protection without the vulnerabilities that plague traditional logic-locking.

Satisfiability-based attack (SAT) resilience

Because the Chameleon eFPGA is hidden within the ASIC fabric, the attacker must simultaneously guess both the logic mapping and the routing configuration inside a regular, highly-flexible fabric, the search space explodes compared with traditional gate-locking.

oracle-guided SAT solvers take impractical time when hard cycles and large key-spaces are introduced

Hardware redaction flow: original marked RTL converted to redacted RTL via eFPGA generation flow, then integrated as eFPGA blocks in the ASIC layout