Eliminate supply chain attacks – from source to silicon, secrecy is synthesized into your ASIC
Our secure-by-design flow keeps your intellectual property protected and in your hands. The result is a NIST-compliant ITAR-friendly bit-stream that can be programmed on-shore, transported openly, and trusted in the field.
When paired with an industry proven hardware state machine (HSM) IP, a best in-class-root of trust can be established to protect the configuration bit stream.
Furthermore, securing a bitstream with industry-leading PUF (physically unclonable function) IP allows for device bitstream locking.
In-field reprogrammability enables a unique and dynamic solution to address digital side channel attacks.
Discover how our secure-by-design flow protects your intellectual property
Our open-source, standards-based SDK turns your Verilog into a signed, place-and-routed netlist without ever touching a third-party macro.
The output is a software synthesizable RTL wrapper that drops straight into your ASIC flow—no black-box license servers, no foundry lock-in, no surprises at tape-out.
Avoids any IP leakage – no need for Chameleon review or sign-off
Explore our open-source software tool suite and design flow
Open-source tools = no vendor lock in or obsolescence
Chameleon eFPGA-based redaction gives IP owners a document-style “black-bar” capability for hardware: critical pieces are simply missing from the delivered gate-level description, yet can be re-instated in the field, delivering strong reverse-engineering protection without the vulnerabilities that plague traditional logic-locking.
Because the Chameleon eFPGA is hidden within the ASIC fabric, the attacker must simultaneously guess both the logic mapping and the routing configuration inside a regular, highly-flexible fabric, the search space explodes compared with traditional gate-locking.
oracle-guided SAT solvers take impractical time when hard cycles and large key-spaces are introduced
The most vulnerable parts of a computer chip to radiation effects are flip-flops
For proton-dominated space environments Chameleon eFPGAs meet or exceed the error-rate of legacy rad-hard FPGAs or solutions based upon triple modular redundancy while shrinking the configuration cell area by roughly an order of magnitude.
Based on a 22nm test chip developed in conjunction with Sandia, at 0.18 × the area of TMR, the Chameleon tile reaches the same “zero visible upsets” level up to at least 4 × 10¹² cm⁻²—equivalent to > 10 krad(Si) TID and > 100 years in LEO behind 5 mm Al shielding
View radiation-hardened eFPGA white papers and technical details
Chameleon test chips are the physical proof that our synthesized eFPGA soft-IP closes timing, meets power and yields in volume.
Fabricated at Global Foundries, TSMC, and Intel semiconductor fabs processes, each vehicle was verified with full RTL-to-bitstream regression enabling customers to drop the same RTL into their own ASIC flow with zero foundry risk.