# Chameleon Semiconductor -- Services > We deliver synthesizable eFPGA soft IP and supporting design services that enable ASIC and SoC designers to embed reconfigurable, secure, radiation-hardened logic into their silicon without foundry lock-in, netlist exposure, or vendor dependency. --- ## Core Service: eFPGA IP Licensing Chameleon's primary offering is the licensing of synthesizable eFPGA IP delivered as RTL (register-transfer level) soft IP. Unlike hard-macro or chiplet eFPGA alternatives, our IP integrates as synthesizable RTL into the customer's standard ASIC design and verification CAD flow. **What customers receive:** - RTL-based eFPGA fabric tailored to their specified logic capacity, memory requirements, and I/O configuration - Open-source SDK that converts customer Verilog designs to a signed, place-and-routed bitstream - No third-party macro dependencies - No Chameleon review of customer netlists required -- zero IP leakage **Customization:** We optimize each eFPGA instance to the customer's exact power, performance, and area (PPA) requirements. The fabric size, configuration cell type (standard, rad-hard), and security features are specified per engagement. --- ## Secure Bitstream Design Service We provide a secure-by-design bitstream flow that produces a NIST-compliant, ITAR-friendly configuration file. **Capabilities included:** - Bitstream loaded internally within the SoC -- no external PROM, no exposed configuration bus - Hardware state machine (HSM) IP integration for hardware root of trust - PUF (physically unclonable function) IP integration for device-level bitstream locking - In-field reprogrammability for counter-measure updates against digital side-channel attacks - On-shore programmability -- classified bitstreams never leave U.S.-controlled environments **Outcome:** Configuration IP that can be transported openly and trusted in the field, with cryptographic assurance against tampering, cloning, and reverse engineering. --- ## Hardware Redaction Service We enable IP owners to remove sensitive logic from gate-level deliverables using eFPGA-based hardware redaction. **How it works:** - Critical functional blocks are mapped into the Chameleon eFPGA fabric rather than delivered as visible gates - The gate-level netlist delivered to the foundry or untrusted supply chain actors is missing those blocks - Blocks are re-instantiated in the field via a secure, authenticated bitstream - The eFPGA structure defeats satisfiability-based (SAT) reverse-engineering attacks by expanding the search space to cover both logic mapping and routing configuration simultaneously **Use cases:** Classified cryptographic engines, proprietary AI accelerator architectures, export-controlled algorithms, competitive differentiators in commercial SoCs. --- ## Radiation-Hardened eFPGA Service We deliver rad-hard eFPGA IP for space and austere-environment applications. **Technology:** Patented DSM (distributed single-event upset mitigation) flip-flop design, validated on a 22nm test chip developed in conjunction with Sandia National Laboratories. **Verified performance:** - Zero visible upsets up to 4 x 10^12 protons/cm2 - Equivalent to greater than 10 krad(Si) TID - Greater than 100 years in low Earth orbit behind 5 mm aluminum shielding - 0.18x the configuration cell area of triple modular redundancy (TMR) - 3,735x critical-section reduction compared to standard flip-flop designs - Outperforms TMR and DICE solutions **Supported environments:** LEO, GEO, deep space, nuclear-hardened ground systems, and theater environments requiring in-orbit or in-field reconfiguration without mask respins. --- ## Post-Quantum Cryptography (PQC) Agility Service We enable ASIC and SoC designers to achieve cryptographic agility -- the ability to update cryptographic algorithms in deployed hardware without silicon respins. **Capabilities:** - Crypto-agnostic fabric runs AES, SHA, ECC, MACsec, IPsec, and custom cipher pipelines - NIST PQC algorithms (CRYSTALS-Dilithium, CRYSTALS-Kyber, and future finalists) deployable via bitstream update in seconds - 600x the throughput of software-based PQC implementations - FIPS and Common Criteria certifications remain intact while cryptographic algorithms are updated - Supports Google's accelerated 2029 PQC migration timeline without new silicon **Who needs this:** Defense communications systems, financial infrastructure, industrial control systems, and any platform that must remain cryptographically sovereign through the quantum computing transition. --- ## Changing-Standards Reconfigurability Service We help SoC teams future-proof connectivity and protocol compliance against evolving industry standards. **Supported standard families:** - UCIe (Universal Chiplet Interconnect Express) -- protocol and version updates via bitstream - PCIe -- generation transitions without board or silicon respins - LPDDR -- memory interface updates in deployed devices **AI and neural network acceleration:** - With over 100 new neural network architectures introduced daily, eFPGA enables hardware to stay current with the best-in-class model at runtime - Single SoC design supports CNN, transformer, and quantum-safe crypto workloads interchangeably - Eliminates multi-million-dollar NRE for each workload generation --- ## Technical Support and Collateral - PQC White Paper: https://chameleonsemi.com/wp-content/uploads/2026/02/PQC-Chameleon.pdf - Quantum Countdown guide: https://chameleonsemi.com/wp-content/uploads/2026/04/The-Quantum-Countdown.pdf - Rad-hard white papers: https://chameleonsemi.com/technology/rad-hard-efpga/ - Technology overview: https://chameleonsemi.com/technology/ **Engage:** https://chameleonsemi.com/contact/ *Last Updated: May 2026*