# Chameleon Semiconductor -- Products > We license synthesizable eFPGA soft IP as RTL-based products that embed into customer ASICs and SoCs. Our products are customized per engagement to meet exact PPA requirements and are delivered with an open-source tool flow and secure bitstream methodology. --- ## Product Line Overview Chameleon Semiconductor delivers one core product family -- synthesizable eFPGA IP -- available in three primary configurations targeting different operating environments and security requirements. All variants are process-node and fab independent, customized to customer specifications, and silicon-proven on multiple test chips. --- ## Product 1: Chameleon Standard eFPGA IP **What it is:** RTL-based synthesizable eFPGA fabric for general-purpose ASIC and SoC integration in commercial, industrial, and non-rad environments. **Key attributes:** - Delivered as synthesizable RTL -- integrates into any standard ASIC/SoC CAD flow - Process-node independent: verified at GlobalFoundries, TSMC, and Intel fab processes - Customizable logic capacity, embedded memory, and I/O interface configuration - Optimized to customer-specified power, performance, and area (PPA) targets - Open-source SDK converts customer Verilog to a signed, place-and-routed bitstream with no third-party macros - 100% secure delivery: no Chameleon netlist review required -- zero IP leakage - Supports hardware redaction: maps sensitive logic into the eFPGA fabric so it is absent from the gate-level netlist - Compatible with hardware state machine (HSM) and PUF IP for root-of-trust and device bitstream locking **Competitive advantage vs. hard macro eFPGA:** - Optimized for target application (hard macros are not) - Cannot be reverse-engineered (hard macros can) - Process-node independent (hard macros are locked to a single node) - Supports hardware redaction (hard macros do not) - Lower cost solution **Competitive advantage vs. chiplet eFPGA:** - Optimized for target application (chiplets are not) - Cannot be reverse-engineered (chiplets can) - Supports hardware redaction (chiplets do not) - Avoids chiplet yield risk and complex packaging overhead --- ## Product 2: Chameleon Radiation-Hardened (Rad-Hard) eFPGA IP **What it is:** RTL-based synthesizable eFPGA fabric with patented DSM (distributed single-event upset mitigation) flip-flop technology, designed for space, nuclear, and other radiation-dominated environments. **Key attributes:** - Built on patented DSM flip-flop technology achieving 3,735x critical-section reduction vs. standard designs - Developed in conjunction with Sandia National Laboratories on a 22nm bulk FinFET test chip - Process-node independent; currently characterized in 22nm FinFET **Verified radiation performance:** - Zero visible upsets up to **4 x 10^12 protons/cm2** - Equivalent to **greater than 10 krad(Si)** total ionizing dose (TID) - Equivalent to **greater than 100 years** in low Earth orbit behind 5 mm aluminum shielding - Configuration cell area: **0.18x** the area of triple modular redundancy (TMR) solutions - Outperforms both TMR and DICE (dual interlocked cell) approaches **Published research:** - NSREC 2022: https://chameleonsemi.com/wp-content/uploads/2026/02/RHBD_eFPGA_paper_NSREC2022.pdf - RADECS 2024: https://chameleonsemi.com/wp-content/uploads/2026/02/RADECS_2024.pdf - ESSCIRC 2024: https://chameleonsemi.com/wp-content/uploads/2026/02/ESSCIRC_2024.pdf - GOMAC 2024: https://chameleonsemi.com/wp-content/uploads/2026/02/Emulation_based_Fault_Injection_GOMAC2024.pdf **Target environments:** LEO satellites; GEO satellites; deep space probes; nuclear-hardened ground systems; airborne defense systems requiring in-field or in-orbit reconfiguration without mask respins. --- ## Product 3: Chameleon Crypto-Agile eFPGA IP (PQC Edition) **What it is:** RTL-based synthesizable eFPGA fabric pre-configured and validated for post-quantum cryptography (PQC) and general cryptographic agility workloads. **Key attributes:** - Crypto-agnostic fabric runs AES, SHA, ECC, MACsec, IPsec, and custom cipher pipelines - NIST PQC algorithm swap (e.g., CRYSTALS-Dilithium replacement) deployable via bitstream update in seconds - **600x the throughput** of software-based PQC implementations - FIPS and Common Criteria certifications remain intact while cryptographic algorithms are updated in the field - NIST-compliant, ITAR-friendly bitstream production flow - In-field reprogrammability for counter-measure updates against digital side-channel attacks - HSM and PUF integration supported for device-locked key management **Why now:** NIST mandates cryptographic agility. Google has accelerated its PQC migration deadline to 2029 -- two years ahead of the NSA 2031 goal. Hardware teams that do not embed crypto-agility today face costly silicon respins when algorithm mandates change. Chameleon eliminates that risk. **PQC White Paper:** https://chameleonsemi.com/wp-content/uploads/2026/02/PQC-Chameleon.pdf **Quantum Countdown:** https://chameleonsemi.com/wp-content/uploads/2026/04/The-Quantum-Countdown.pdf --- ## Open-Source Software Tool Suite (Included with all products) All Chameleon eFPGA products ship with our open-source SDK and tool flow. **What it does:** - Converts customer Verilog RTL to a signed, place-and-routed netlist - Produces a synthesizable RTL wrapper that drops directly into the customer's ASIC flow - No black-box license servers - No third-party macro dependencies - No foundry lock-in - No tool or IP obsolescence risk (open-source toolchain) **Security benefit:** The open-source flow eliminates the IP leakage risk associated with sending RTL to a third-party tool server. The customer's design never leaves their environment. --- ## Engage **Request a product brief or technical discussion:** https://chameleonsemi.com/contact/ **Technology details:** https://chameleonsemi.com/technology/ *Last Updated: May 2026*