# Chameleon Semiconductor Website: https://chameleonsemi.com Language: en (UTF-8) Charset: UTF-8 Generated: 2026-09-08T13:22:57-07:00 --- # Chameleon Semiconductor > We are the only U.S.-based provider of synthesizable embedded FPGA (eFPGA) soft IP, delivering hardware security, cryptographic agility, and post-deployment reconfigurability to mission-critical aerospace, defense, and advanced computing markets – without silicon respins, foundry lock-in, or IP leakage. --- ## Who We Are Chameleon Semiconductor is a US-based semiconductor IP company founded in 2024 to commercialize synthesized eFPGA technology originally developed from 2018 onward within the Electrical and Computer Engineering department at Carnegie Mellon University under Professor Ken Mai. After approximately five years of intensive R&D, we launched with a focused mission: give hardware the adaptability of software, without compromising security or performance. We deliver RTL-based synthesizable eFPGA soft IP that embeds directly into customer ASICs and SoCs. Unlike embedded hard macros or chiplet solutions, our IP is process-node independent, fab independent, optimized for the target application, and invisible to reverse engineering. It drops into standard ASIC CAD flows and produces zero IP leakage – no Chameleon review or sign-off of customer netlists is required. Our technology has been silicon-proven on multiple test chips fabricated at GlobalFoundries, TSMC, and Intel semiconductor fabs across multiple process nodes. --- ## Core Business Facts - **Company type:** Semiconductor IP company – synthesizable eFPGA soft IP - **Founded:** 2024 - **R&D origins:** Carnegie Mellon University ECE department, beginning 2018 - **Technology:** RTL-based synthesizable eFPGA – process-node and fab independent - **Primary differentiator:** Only U.S.-based provider of synthesizable eFPGA soft IP - **Silicon proven:** Multiple test chips at GlobalFoundries, TSMC, and Intel fabs - **Key performance:** 600x throughput over software for post-quantum cryptography workloads - **Rad-hard performance:** Zero visible upsets up to 4 x 10^12 protons/cm2; 0.18x the area of TMR; greater than 100 years LEO survivability behind 5 mm Al shielding - **Sandia partnership:** Rad-hard 22nm test chip developed in conjunction with Sandia National Laboratories - **Publications:** NSREC 2022, RADECS 2024, ESSCIRC 2024, GOMAC 2024 - **IP security:** 100% secure delivery – no manual netlist review or intervention required - **Tool flow:** Open-source SDK converts Verilog to signed, place-and-routed netlist without third-party macros - **Compliance:** NIST-compliant, ITAR-friendly bitstream; FIPS and Common Criteria compatible --- ## What We Do We license synthesizable eFPGA soft IP that customers embed into their own ASICs and SoCs. Our IP turns fixed silicon into reconfigurable silicon – enabling post-deployment updates to algorithms, cryptography, standards compliance, and workload acceleration without requiring a new mask set or silicon respin. **Core capabilities:** - **Synthesizable eFPGA IP:** RTL-based soft IP delivered as a synthesizable wrapper that integrates into any standard ASIC design flow. Process-node and fab independent. Optimized to the customer's exact power, performance, and area (PPA) requirements. - **Secure bitstream:** NIST-compliant, ITAR-friendly configuration bitstream programmable onshore. Supports hardware state machine (HSM) integration for root of trust. Supports PUF (physically unclonable function) integration for device-level bitstream locking. In-field reprogrammability addresses digital side-channel attacks. - **Hardware redaction:** Critical IP blocks are absent from the gate-level netlist deliverable and can be re-instantiated in the field. Resists satisfiability-based (SAT) attack tools, which face impractical search times against Chameleon's large key-space and hard-cycle structure. - **Radiation-hardened eFPGA:** Patented DSM (distributed single-event upset mitigation) flip-flop technology achieves 3,735x critical-section reduction. Outperforms TMR and DICE solutions at 0.18x the area. Suitable for LEO, GEO, deep space, and nuclear-hardened environments. - **Open-source tool flow:** Our SDK converts Verilog RTL to a signed, place-and-routed netlist with no third-party macros, no black-box license servers, and no foundry lock-in. Avoids tool and IP obsolescence. --- ## Markets We Serve **Aerospace and Defense** We are the industry's only onshore provider of RTL-based eFPGA solutions for defense. Classified algorithms stay on U.S. soil. Rad-hard eFPGA updates occur in orbit or in theater without mask respins. Our ITAR-friendly supply chain removes the compliance friction that foreign-sourced eFPGA solutions create for prime contractors and program offices. **Security and Post-Quantum Cryptography** Our crypto-agnostic fabric runs AES, SHA, ECC, MACsec, IPsec, and custom ciphers. A Chameleon eFPGA bitstream can swap CRYSTALS-Dilithium for a new NIST PQC finalist in seconds, while delivering 600x the throughput of software-based implementations. FIPS and Common Criteria certifications remain intact while hardware stays fixed. Google has accelerated its PQC migration target to 2029; Chameleon enables hardware teams to meet that timeline without a silicon respin. **Advanced Computing** One eFPGA-enabled SoC replaces entire accelerator families, collapsing SKUs and simplifying supply chains. A smartNIC that accelerates MACsec at terabit speeds today can integrate post-quantum key exchange tomorrow and add homomorphic encryption the year after – all on the same validated silicon. With over 100 new neural networks introduced daily, eFPGA keeps AI hardware current without board respins. **Changing Standards and Requirements** UCIe, PCIe, and LPDDR connectivity updates deploy via bitstream, not silicon respins. Late-breaking standards changes that would otherwise trigger million-dollar mask costs and schedule delays become firmware-style releases. Hardware launched compliant remains compliant for decades. --- ## Technology Differentiators **vs. Embedded Hard Macro eFPGA:** - Chameleon is optimized for the target application; hard macros are not - Chameleon cannot be reverse-engineered; hard macros are subject to RE - Chameleon is process-node independent; hard macros are locked to a single node - Chameleon supports hardware redaction; hard macros do not - Chameleon is the lowest-cost solution **vs. Chiplet-Based eFPGA:** - Chameleon is optimized for the target application; chiplets are not - Chameleon cannot be reverse-engineered; chiplets are subject to RE - Chameleon supports hardware redaction; chiplets do not - Chiplet solutions face low yield and complex packaging; Chameleon avoids both **vs. Proprietary Tool Flows:** - Chameleon uses an open-source SDK with no license-server dependencies - No vendor lock-in; no tool or IP obsolescence risk - Customer RTL never touches a third-party macro or requires Chameleon review --- ## Leadership and Authority **Geoff Rodgers, CEO** More than 25 years of semiconductor and EDA industry leadership. Senior sales and go-to-market roles at Synopsys, Cadence, PDF Solutions, and multiple successful startups. Deep expertise in commercializing advanced IP technologies. **Ken Mai, CTO** Professor of Electrical and Computer Engineering at Carnegie Mellon University. Directs research in VLSI design, reconfigurable computing, and integrated circuits for austere environments. Led over seven years of Chameleon eFPGA R&D within his CMU research group. **Robert Bielby, VP Marketing** More than 30 years of semiconductor industry leadership at Altera, Xilinx, LSI Logic, Micron, and Untether AI. Spans P&L management, corporate strategy, product definition, and vertical marketing. **Research and Recognition:** - Peer-reviewed publications: NSREC 2022, RADECS 2024, ESSCIRC 2024, GOMAC 2024 - Sandia National Laboratories partnership (22nm rad-hard eFPGA test chip) - Featured in Semi Wiki CEO interview, May 2026 - PQC White Paper and Quantum Countdown guide publicly available --- ## Contact **Website:** https://chameleonsemi.com **Contact:** https://chameleonsemi.com/contact/ **Technology:** https://chameleonsemi.com/technology/ **Markets:** https://chameleonsemi.com/markets/ **News and Expertise:** https://chameleonsemi.com/news-and-expertise/ **PQC White Paper:** https://chameleonsemi.com/wp-content/uploads/2026/02/PQC-Chameleon.pdf *Last Updated: May 2026* # Detailed Content ## Posts ### Why Your Edge AI Accelerator Will Be Obsolete Before It Ships - **URL:** https://chameleonsemi.com/open-source-fpga-tool-flow/ - **Published:** 2026-07-13 - **Modified:** 2026-07-23 - **Author:** Robert Bielby **Summary:** Edge AI evolves faster than silicon. Chameleon embeds a reconfigurable eFPGA into standard ASIC flows (16nm and 22nm) so you reconfigure, not respin the die. **Content:** If you’re designing an edge AI processor today, you’re already behind. Not because your team isn’t talented, but because the neural network you’re targeting will almost certainly be replaced by something better, smaller, or completely different before your silicon ever reaches a customer.   The AI landscape is shifting faster than any hardware roadmap can keep pace with. CNNs dominated vision tasks for years, then R-CNNs added region-of-interest operations, Vision Transformers introduced self-attention blocks, and now LLMs are pushing into edge inference with masked self-attention and KV-cache streaming. Each of these architectures demands a fundamentally different compute, memory, and precision profile.   A CNN accelerator is built for convolution-heavy, weight-stationary, 8-bit integer workloads. A ViT needs 16-bit floating point, is numerically sensitive to attention-map precision, and thrives on token-level parallelism. An LLM decode phase is dominated by general matrix-vector multiply, serial token generation, and KV-cache streaming that is append-only and precision-critical. A fixed accelerator architecture designed for any one of these will fail across the spectrum. Our own analysis makes this painfully clear: operator mix, compute granularity, memory patterns, parallelism, and precision needs all diverge dramatically across these workloads. Rigid accelerators succeed for specific models, but they fail when the model evolves – and evolve it will.   This is where embedded FPGA changes the equation entirely. Chameleon’s eFPGA is not a compromise between flexibility and efficiency; it is a tunable compute engine that lets architects configure precision, deterministic data movement, and reprogrammability to match the neural network at hand, not the one that was fashionable when the tapeout started. With configurable logic blocks, BRAM, DSP tiles, and I/O all synthesized as soft IP directly into the ASIC, the same silicon can run a CNN today, a ViT next year, and an LLM inference engine the year after – all without requiring a respin.   Our test chips have demonstrated this in practice: a 16nm 2K-LUT fabric running at 630 MHz, and a heterogeneous 22nm architecture with BRAM, DSP, and CLB blocks hitting 561 MHz. That is performance on par with commercial FPGAs, but embedded inside a standard ASIC flow with zero new tools and zero new risk. The market math is compelling. By 2030, diverse AI and ML workloads alone represent a $300 million serviceable addressable market for eFPGA-based solutions. But the real value is not the market size – it is the insurance policy. A hardened ASIC with an eFPGA block is a hedge against algorithmic obsolescence.   When the next transformer variant drops, or when a new quantization scheme emerges, or when a customer demands support for a model you never anticipated, you reconfigure the bitstream, not the silicon. In an industry where 4,500 ASICs are taped out annually and many are obsolete before they ship, that flexibility is not a luxury. It is survival.   The edge AI race is not won by the team that builds the fastest accelerator for today’s model. It is won by the team that builds silicon flexible enough to run tomorrow’s model without starting over. eFPGA… --- ### Chameleon Semiconductor - Featured in Semi Wiki - **URL:** https://chameleonsemi.com/chameleon-semiconductor-featured-in-semi-wiki/ - **Published:** 2026-05-10 - **Modified:** 2026-05-10 - **Author:** Robert Bielby **Summary:** Chameleon CEO, Geoff Rodgers was recently interviewed by Semi Wiki regarding the company and the unique solution offerings. **Content:** Chameleon Semiconductor, led by industry veterans, offers a “design-for-change” model using embedded FPGA (eFPGA) technology to address the rigidity of traditional ASIC and SoC designs. By delivering eFPGA as synthesizable soft IP rather than fixed hard macros, the company provides flexibility and portability, allowing hardware to adapt to evolving standards and security threats post-deployment. As a US-based provider, Chameleon targets high-security sectors, including aerospace, defense, and AI chiplets, utilizing open-source tool flows to enable post-silicon programmability without respin costs. Read the complete article here --- ### Chameleon: The Missing Link in the UCIe Ecosystem - **URL:** https://chameleonsemi.com/chameleon-is-the-essential-enabling-technology-for-ucie-and-the-chiplet-marketplace/ - **Published:** 2026-05-05 - **Modified:** 2026-07-23 - **Author:** Geoff Rodgers **Summary:** UCIe standardizes chiplet die-to-die links, but real interoperability needs flexibility above the PHY. Chameleon eFPGA brings secure, reconfigurable logic. **Content:** Chameleon Semiconductor’s eFPGA enables UCIe chiplet interoperability by adding secure, reconfigurable intelligence above the PHY layer. This flexibiity reduces integration risk, avoids ASIC respins, and accelerates time‑to‑market in a multi‑vendor chiplet ecosystem. UCIe Blog FinalDownload --- ### Accelerated PQC Timeline Requires Hardware Agility - **URL:** https://chameleonsemi.com/crypto-agility-pqc-ready-efpga/ - **Published:** 2026-04-15 - **Modified:** 2026-05-06 - **Author:** Robert Bielby **Summary:** The quantum computing era is approaching. Learn how cryptographic agility, enabled by Chameleon Semiconductor's eFPGA, is the key to staying ahead of the curve. **Content:** The digital security landscape shifted dramatically last month when Google announced an accelerated timeline for Post-Quantum Cryptography (PQC) migration, moving its target completion date to 2029. This shift, two years ahead of the NSA’s 2031 goal, is a response to rapid advancements in quantum hardware and error correction that could see current encryption broken much sooner than previously thought. For industries ranging from finance to critical infrastructure, Google’s “wake-up call” transforms PQC from a distant research project into an immediate engineering priority. The Quantum CountdownDownload --- ### The Quantum Threat is Here - **URL:** https://chameleonsemi.com/pqc-cryptography/ - **Published:** 2026-04-09 - **Modified:** 2026-04-14 - **Author:** Robert Bielby **Summary:** The quantum computing revolution isn’t coming; it’s already knocking at our door. Shor’s algorithm threatens to dismantle RSA and ECC encryption in mere hours once cryptographically relevant quantum computers (CRQCs)... **Content:** The quantum computing revolution isn’t coming; it’s already knocking at our door. Shor’s algorithm threatens to dismantle RSA and ECC encryption in mere hours once cryptographically relevant quantum computers (CRQCs) arrive, while Grover’s algorithm halves the security of symmetric encryption. For industries with long lifecycle products including automotive, aerospace, defense, and critical infrastructure – this isn’t a distant concern. It is almost guaranteed that a vehicle or satellite launched today with fixed-function cryptographic hardware will be operational well past “Q-Day,” the moment quantum supremacy renders classical encryption obsolete. The stakes couldn’t be higher: without agility, we’re not just risking data breaches, we’re guaranteeing them. The Quantum Threat Is HereDownload --- ### "Secure by design" is a myth - **URL:** https://chameleonsemi.com/efpga-future-flexible-silicon/ - **Published:** 2026-01-04 - **Modified:** 2026-07-23 - **Author:** Robert Bielby **Summary:** IEEE HOST 2025 showed the Adams Bridge PQC accelerator vulnerable to key extraction. Chameleon eFPGA enables runtime defenses against side-channel attacks. **Content:** The semiconductor industry’s march toward post-quantum cryptography (PQC) has taken a significant step forward with the Caliptra Root of Trust (RoT) initiative – an open-source silicon security framework developed under the CHIPS Alliance. At the heart of Caliptra’s cryptographic engine sits Adams Bridge, a hardware accelerator designed by Microsoft and other consortia members to implement the NIST-standardized ML-DSA (Module-Lattice-Based Digital Signature Algorithm) and ML-KEM (Module-Lattice-Based Key Encapsulation Mechanism) schemes. Adams Bridge represents a critical piece of infrastructure: it is the first open-source, industry-scale PQC accelerator targeting real-world deployment in hyperscale SoCs, offering unified acceleration for both signature and key-encapsulation operations within a single architecture. The Bold Claims and the Harsh Reality Adams Bridge was architected with side-channel resistance as a key design objective. The accelerator embeds hardware-level countermeasures including masking, coefficient-level shuffling, and constant-time execution, with empirical TVLA (Test Vector Leakage Assessment) evaluation performed across one million traces to validate the elimination of first-order leakage in critical datapaths. Caliptra’s threat model explicitly focuses on non-profiled, multi-trace attacks such as Correlation Power Analysis (CPA), reasoning that Adams Bridge’s deployment context – embedded within power-dense, high-activity hyperscale SoCs – would inherently suppress the signal-to-noise ratio (SNR) required for more sophisticated profiled or SPA-style attacks. The design philosophy was clear: in a noisy environment, statistical averaging through CPA is the realistic adversarial vector, and the countermeasures were tuned accordingly. When Theory Meets Practice The problem with threat models is that they are only as strong as the assumptions they rest upon. In late 2024, researchers at Florida Atlantic University (FAU) demonstrated a successful Correlation Power Analysis (CPA) attack against Adams Bridge recovering secret keys in just 10,000 traces – a remarkably low bar for a design that claims million-trace TVLA validation. The attack targeted the secret-key multiplication step within the ML-DSA signature generation path, exploiting the deterministic variant of the algorithm that Caliptra’s DICE certificate flow requires for reproducible identity derivation. This is not a theoretical vulnerability; it is a proven, practical key extraction against a production-intent PQC accelerator. The FAU work, subsequently published at IEEE HOST 2025, exposed a fundamental tension: while Adams Bridge’s masking and shuffling are architecturally sound, the reality of physical implementation – particularly the movement and deserialization of plaintext secret keys during early pipeline stages—creates exploitable leakage windows that statistical countermeasures alone cannot fully close. Pre-silicon analysis has further confirmed that the biggest TVLA spikes occur precisely when the secret key is being moved about and transformed. The eFPGA Imperative: Agility as the Ultimate Countermeasure This is where Chameleon Semiconductor’s eFPGA technology fundamentally changes the equation. Static side-channel countermeasures—masking, shuffling, constant-time design – are necessary but insufficient because they are frozen at tape-out. Once an attacker characterizes the leakage profile of a fixed silicon implementation, the attack can be refined, optimized, and scaled. Chameleon’s eFPGA breaks this asymmetry by enabling runtime reconfiguration of the cryptographic datapath. Chameleon’s synthesized, software-defined eFPGA IP allows the physical implementation of sensitive operations – NTT butterflies, pointwise multiplications, secret-key deserialization- to be dynamically… --- ### Locking It Down: The Importance of a Secure Bitstream - **URL:** https://chameleonsemi.com/importance-secure-bitstream/ - **Published:** 2026-01-03 - **Modified:** 2026-07-23 - **Author:** Ken Mai **Summary:** The bitstream is the key to your FPGA. If it is intercepted, cloned, or reverse-engineered, your IP is at risk. See why a secure, encrypted bitstream matters. **Content:** The bitstream is the file that contains the configuration data for an FPGA or eFPGA. It defines the logic, the interconnects—everything that makes the hardware perform its specific function. Protecting this bitstream is therefore critical to protecting your intellectual property. In a traditional FPGA, the bitstream is often stored in an external PROM, creating a significant vulnerability. Chameleon’s eFPGA technology addresses this from the ground up. Because the eFPGA fabric is embedded within the SoC, there is no external device to probe. The bitstream is loaded internally, and can be protected with industry-standard encryption and on-chip key storage. This “hidden-in-plain-sight” approach makes it incredibly difficult for an attacker to intercept or tamper with the configuration data. Furthermore, by pairing the eFPGA with a hardware state machine (HSM) or a physically unclonable function (PUF), you can establish a hardware root of trust and even lock a bitstream to a specific device. This ensures that your IP can only run on authorized hardware, preventing cloning and unauthorized use. It’s a comprehensive approach to security that starts with protecting the very essence of your design—the bitstream. --- ### The Adaptive Edge: How eFPGA is Unlocking Flexible AI Workloads - **URL:** https://chameleonsemi.com/efpga-flexible-ai-workloads/ - **Published:** 2026-01-02 - **Modified:** 2026-07-23 - **Author:** Ken Mai **Summary:** AI models and algorithms change daily, a real challenge for edge devices. See how eFPGA gives the hardware flexibility to run diverse, evolving AI workloads. **Content:** Artificial intelligence is no longer confined to the data center. From smart cameras to autonomous vehicles, AI is moving to the edge. But edge AI presents a unique set of challenges. Power is limited, latency is critical, and the AI models themselves are constantly evolving. An ASIC designed for one type of neural network may be inefficient for the next. This is where the adaptability of eFPGA becomes a powerful advantage. By implementing the neural network accelerators in a reconfigurable fabric, you can update the hardware to optimize for new models, different data types, or changing performance requirements. If a new, more efficient quantization method emerges, you can update the eFPGA to support it. If you need to switch from a CNN to a transformer model, you can reconfigure the hardware to match. This flexibility allows you to build a single piece of hardware that can adapt to a wide range of AI workloads over its entire product life. It eliminates the risk of hardware obsolescence and allows you to continuously deploy the most efficient and powerful AI models to your edge devices. It’s the key to building truly intelligent and future-proof systems. --- ### Trust in the Chain: Securing the Semiconductor Supply Chain with Onshore eFPGA - **URL:** https://chameleonsemi.com/securing-semiconductor-supply-chain/ - **Published:** 2026-01-01 - **Modified:** 2026-07-23 - **Author:** Ken Mai **Summary:** The semiconductor supply chain is full of risk, from design to fab. See how an onshore, RTL-based eFPGA flow builds trust for your critical designs. **Content:** The journey of a microchip from design to deployment is a long and complex one, often spanning multiple countries and companies. Each step in this global supply chain represents a potential point of vulnerability. How can you be sure your design files haven’t been tampered with? How can you prevent your IP from being stolen or cloned during manufacturing? Chameleon Semiconductor was founded on the principle of providing a secure, trustworthy, and onshore solution. Our eFPGA technology is delivered as RTL source code, which you synthesize into your own ASIC within your own secure environment. There is no black-box IP, no manual netlist intervention required. The entire flow is transparent and auditable. This “hidden-in-plain-sight” integration means that the most sensitive parts of your design never have to leave your control. The final, encrypted bitstream can be loaded onto the device in a secure, onshore facility, satisfying even the strictest ITAR and supply-chain security mandates. It’s a fundamental shift in how we think about silicon security, moving from a model of distributed risk to one of centralized, verifiable trust. --- ## Pages ### Privacy Statement (US) - **URL:** https://chameleonsemi.com/privacy-statement-us/ - **Published:** 2026-06-23 - **Modified:** 2026-06-23 - **Author:** david@boomcycle.com **Summary:** This privacy statement was last changed on June 24, 2026, last checked on June 24, 2026, and applies to citizens and legal permanent residents of the United States.In this privacy... **Content:** This privacy statement was last changed on June 24, 2026, last checked on June 24, 2026, and applies to citizens and legal permanent residents of the United States. In this privacy statement, we explain what we do with the data we obtain about you via https://chameleonsemi.com. We recommend you carefully read this statement. In our processing we comply with the requirements of privacy legislation. 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Third-party websites This privacy statement does not apply to third-party websites connected… --- ### Opt-out preferences - **URL:** https://chameleonsemi.com/opt-out-preferences/ - **Published:** 2026-06-23 - **Modified:** 2026-06-23 - **Author:** david@boomcycle.com **Summary:** This page was last changed on June 24, 2026, last checked on June 24, 2026 and applies to citizens and legal permanent residents of the United States. 1. IntroductionOur website,... **Content:** This page was last changed on June 24, 2026, last checked on June 24, 2026 and applies to citizens and legal permanent residents of the United States. 1. Introduction Our website, https://chameleonsemi.com (hereinafter: "the website") uses cookies and other related technologies (for convenience all technologies are referred to as "cookies"). Cookies are also placed by third parties we have engaged. In the document below we inform you about the use of cookies on our website. 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Read more about Complianz Sharing data This data is not shared with third parties. For more information, please… --- ### Proven Technology - **URL:** https://chameleonsemi.com/technology/proven-technology/ - **Published:** 2026-02-19 - **Modified:** 2026-05-23 - **Author:** david@boomcycle.com **Summary:** Eight successful test chips across four foundries. Chameleon's silicon-proven eFPGA validated on TSMC and leading fabs from 16nm FinFET to Intel 18A. **Content:** Technology: Proven Technology Eight successful test chips across four foundries Eight successful test chips across four foundries. Our silicon-proven track record spans multiple tapeouts on TSMC, Intel, GlobalFoundries, and Samsung—demonstrating robust design portability and foundry flexibility that de-risks your supply chain. Silicon proven from 16nm FinFET to Intel 18A. Validated performance across leading-edge nodes including 16nm, 22nm, and Intel’s most advanced 18A process—ensuring your eFPGA IP scales with technology roadmaps without architectural compromise. Unmatched process portability for mission-critical designs. Synthesizable soft IP architecture eliminates hard macro lock-in, enabling seamless migration across foundries and nodes to meet ITAR requirements, address supply chain disruptions, and optimize for performance or power as your mission demands. --- ### Changing Requirements - **URL:** https://chameleonsemi.com/markets/changing-requirements/ - **Published:** 2026-01-09 - **Modified:** 2026-05-23 - **Author:** david@boomcycle.com **Summary:** Markets: Changing Requirements Changing Standards: Reconfigurable Silicon That Never Ages Future-proof your design against evolving standards—UCIe, PCIe, and LPDDR connectivity updates deploy via bitstream, not silicon respins. Adapt in-market products... **Content:** Markets: Changing Requirements Changing Standards: Reconfigurable Silicon That Never Ages Future-proof your design against evolving standards—UCIe, PCIe, and LPDDR connectivity updates deploy via bitstream, not silicon respins. Adapt in-market products to late-breaking requirements with reconfigurable hardware that avoids million-dollar mask costs and being late to market. The Chameleon eFPGA transforms obsolescence risk into competitive advantage. Artificial Intelligence With over 100 new neural networks introduced daily, remaining current employing the best-in-class algorithm at speed while protecting your critical IP requires Chameleon eFPGA – no new silicon, no board spin Emerging Standards Standards evolve. Your hardware should too. Whether its recently introduced versions of standards such as UCIe or PCIe Chameleon eFPGA delivers the essential reprogrammability avoiding silicon respins, and obsolescence --- ### Advanced Computing - **URL:** https://chameleonsemi.com/markets/advanced-computing/ - **Published:** 2026-01-09 - **Modified:** 2026-05-23 - **Author:** david@boomcycle.com **Summary:** Markets: Advanced Computing Our eFPGA technology turns hardware into a perpetual asset. One eFPGA-enabled SoC replaces entire accelerator families, collapsing SKUs, simplifying supply chains, and amortizing NRE across algorithmic generations.... **Content:** Markets: Advanced Computing Our eFPGA technology turns hardware into a perpetual asset. One eFPGA-enabled SoC replaces entire accelerator families, collapsing SKUs, simplifying supply chains, and amortizing NRE across algorithmic generations. A smartNIC that accelerates MACsec at terabit speeds today, integrates post-quantum key exchange tomorrow, and adds homomorphic encryption next year—all on the same validated and deployed silicon. This highly flexible hardware investment becomes a perpetual competitive moat. Protect proprietary architectures through hardware redaction and supply-chain-agnostic soft IP Advanced Computing (graphic) --- ### Security / PQC - **URL:** https://chameleonsemi.com/markets/security-pqc/ - **Published:** 2026-01-09 - **Modified:** 2026-05-23 - **Author:** david@boomcycle.com **Summary:** Markets: Security / PQC Crypto-agnostic fabric runs AES, SHA, ECC, MACsec, IPsec, and custom ciphers—update crypto in the field while hardware stays fixed, preserving FIPS and Common Criteria certification. PQC... **Content:** Markets: Security / PQC Crypto-agnostic fabric runs AES, SHA, ECC, MACsec, IPsec, and custom ciphers—update crypto in the field while hardware stays fixed, preserving FIPS and Common Criteria certification. PQC Details and White Paper NIST mandates agility— A Chameleon eFPGA bit-stream can swap CRYSTALS-Dilithium for a new finalist in seconds, while delivering 600× the throughput of software. Get your PQC Whitepaper here --- ### Aerospace & Defense - **URL:** https://chameleonsemi.com/markets/aerospace-defense/ - **Published:** 2026-01-09 - **Modified:** 2026-05-23 - **Author:** david@boomcycle.com **Summary:** The industry's only on-shore RTL-based eFPGA provider for aerospace and defense. Maximum IP security, algorithmic flexibility, and zero foundry lock-in. **Content:** Markets: Aerospace & Defense The industry’s only on-shore provider of RTL-based eFPGA solutions Maximum algorithmic life, maximum IP security, maximum flexibility, zero foundry and process lock-in, with classified compliance that hard macros simply cannot match. Conceal sensitive cryptographic engines and algorithms inside reconfigurable logic, eliminating reverse-engineering risk while maintaining performance. Use Chameleon's eFPGA IP to obscure critical functionality from adversaries and untrusted supply chain actors. Classified algorithms stay on-shore; rad-hard eFPGA updates occur in orbit or theater without a mask re-spin; expanded capabilities without compromise. RAD Hard Delivering radiation-hardened eFPGA IP that meets the most stringent reliability requirements that outperforms TMR and DICE with modest area overhead Our patented DSM flip-flop technology achieves 3,735× critical-section reduction for space and austere environments. Whitepaper: Emulation-based Fault Injection Whitepaper: PQC (more whitepapers coming soon!) --- ### Open Source Software Tool Suite - **URL:** https://chameleonsemi.com/technology/software-tool-suite/ - **Published:** 2026-01-09 - **Modified:** 2026-05-23 - **Author:** david@boomcycle.com **Summary:** Technology: Open Source Software Tool Suite Our open-source, standards-based SDK turns your Verilog into a signed, place-and-routed netlist without ever touching a third-party macro. Specify your exact eFPGA requirements for... **Content:** Technology: Open Source Software Tool Suite Our open-source, standards-based SDK turns your Verilog into a signed, place-and-routed netlist without ever touching a third-party macro. Specify your exact eFPGA requirements for your design. Our software automatically generates the synthesizable RTL and configuration bitstream. Seamlessly integrate into your existing CAD flow with complete control over fabric architecture, resource allocation, and timing constraints. No black-box license servers, no foundry-lock in, no surprises at tape-out. Avoids any IP leakage – no need for Chameleon review or sign-off Built on industry-standard open-source tools including Yosys for synthesis and VPR for place-and-route. Open-tools ensure transparency while eliminating vendor lock-in and obsolescence. Define your exact eFPGA architecture.  Specify the CLB type (4-input or 6-input LUTs), BRAM and DSP mix, and routing resources—via specification files that drive our automated generation flow. Our Chisel-based fabric generator constructs the complete RTL implementation, automatically inserting scan chains for testability and manufacturing validation. VPR-based place-and-route ensures optimal physical implementation, generating configuration bitstreams tuned to your specified fabric topology. Routing resources are fully customizable and automatically optimized to balance interconnect flexibility against die area constraints. The result: a bespoke eFPGA fabric precisely matched to your application’s performance, power, and area requirements—generated automatically from architecture to silicon. Implement your design onto Chameleon eFPGA using an open, automated flow built on industry-standard tools. Synthesize your RTL into LUT netlists using Yosys, the trusted open-source synthesis suite supporting Verilog and System Verilog inputs. Our Python parser bridges synthesis output to VPR, automatically converting netlists into the physical representation required for place-and-route on your custom eFPGA fabric. VPR performs timing-driven placement and routing, optimizing for your specified architecture while generating the configuration bitstream that programs your eFPGA. Verify functional correctness pre-silicon using Cocotb, the Python-based verification framework enabling rapid testbench development and regression testing of mapped designs against golden references. The complete flow—from RTL to verified bitstream—integrates seamlessly into your existing CAD environment without proprietary tool dependencies. Configurable logic blocks arranged in a regular array, interconnected through programmable switch blocks enabling flexible routing topologies. Each logic block contains LUTs, flip-flops, and arithmetic carry chains for efficient implementation of combinational and sequential functions. Switch blocks provide programmable connectivity between adjacent logic blocks, supporting nearest-neighbor and longer-distance routing resources optimized for speed or area. Dedicated I/O blocks (IOBs) interface the eFPGA array to the internal SoC logic. Each logic block (LB) contains eight, 4-input or 6-input basic logic elements (BLEs), interconnected via an internal crossbar switch for highly flexible routing. The BLE supports both registered and unregistered outputs, enabling efficient implementation of pipelined or purely combinational functions. Each LB interfaces to horizontal and vertical routing channels through a programmable connection block, providing access to global interconnect resources. Switch blocks at routing channel intersections interconnect horizontal and vertical wire segments, creating a scalable, mesh-based routing fabric optimized for timing and routability. --- ### Hardware Redaction - **URL:** https://chameleonsemi.com/technology/hardware-redaction/ - **Published:** 2026-01-09 - **Modified:** 2026-05-23 - **Author:** david@boomcycle.com **Summary:** Technology: Hardware Redaction The industry’s best in class technologies combined to deliver the industry’s leading eFPGA solution. Hidden in plain sight Chameleon eFPGA-based redaction gives IP owners a document-style "black-bar"... **Content:** Technology: Hardware Redaction The industry’s best in class technologies combined to deliver the industry’s leading eFPGA solution. Hidden in plain sight Chameleon eFPGA-based redaction gives IP owners a document-style "black-bar" capability for hardware: critical pieces are simply missing from the delivered gate-level description, yet can be re-instated in the field, delivering strong reverse-engineering protection without the vulnerabilities that plague traditional logic-locking. Satisfiability-based attack (SAT) resilience Because the Chameleon eFPGA is hidden within the ASIC fabric, the attacker must simultaneously guess both the logic mapping and the routing configuration inside a regular, highly-flexible fabric, the search space explodes compared with traditional gate-locking. oracle-guided SAT solvers take impractical time when hard cycles and large key-spaces are introduced --- ### Radiation Hardened eFPGA - **URL:** https://chameleonsemi.com/technology/rad-hard-efpga/ - **Published:** 2026-01-09 - **Modified:** 2026-05-23 - **Author:** david@boomcycle.com **Summary:** Technology: Rad Hard eFPGA Delivering radiation-hardened eFPGA IP that meets the most stringent reliability requirements that outperforms TMR and DICE with modest area overhead The most vulnerable parts of a... **Content:** Technology: Rad Hard eFPGA Delivering radiation-hardened eFPGA IP that meets the most stringent reliability requirements that outperforms TMR and DICE with modest area overhead The most vulnerable parts of a computer chip to radiation effects are flip-flops. For proton-dominated space environments Chameleon eFPGAs meet or exceed the error-rate of legacy rad-hard FPGAs or solutions based upon triple modular redundancy while shrinking the configuration cell area by roughly an order of magnitude. Based on a 22nm test chip developed in conjunction with Sandia, at 0.18 × the area of TMR, the Chameleon tile reaches the same "zero visible upsets" level up to at least 4 × 10¹² cm⁻²—equivalent to > 10 krad(Si) TID and > 100 years in LEO behind 5 mm Al shielding White Papers Emulation-based Fault Injection A Radiation Hardened by Design FPGA with Distributed Single Event Upset Sensors, Embedded Error Handler, and 8Mb Embedded MRAM Configuration Storage in 22nm Bulk FinFET CMOS Design and Evaluation of Flip-Flops for eFPGA Configuration Hardening A Soft Error Tolerant Flip-Flop for eFPGA Configuration Hardening in 22nm FinFET Process (more whitepapers coming soon!) --- ### Secure by Design - **URL:** https://chameleonsemi.com/technology/secure-by-design/ - **Published:** 2026-01-09 - **Modified:** 2026-05-23 - **Author:** david@boomcycle.com **Summary:** Eliminate supply chain attacks with Chameleon's secure-by-design eFPGA flow. NIST-compliant IP protection from source to silicon, with hardware root of trust. **Content:** Technology: Secure by Design Eliminate supply chain attacks – from source to silicon, secrecy is synthesized into your ASIC Our secure-by-design flow keeps your intellectual property protected and in your hands. The result is a NIST-compliant ITAR-friendly bit-stream that can be programmed on-shore, transported openly, and trusted in the field. When paired with an industry proven hardware state machine (HSM) IP, a best in-class-root of trust can be established to protect the configuration bit stream Furthermore, securing a bitstream with industry-leading PUF (physically unclonable function) IP allows for device bitstream locking In-field reprogrammability enables a unique and dynamic solution to address digital side channel attacks --- ### About Us - **URL:** https://chameleonsemi.com/about-us/ - **Published:** 2026-01-08 - **Modified:** 2026-05-23 - **Author:** david@boomcycle.com **Summary:** About Chameleon Chameleon is the only U.S.-based provider of synthesizable eFPGA soft IP, delivering hardware security and cryptographic agility and flexibility to accommodate standards changes across a wide spectrum of... **Content:** About Chameleon Chameleon is the only U.S.-based provider of synthesizable eFPGA soft IP, delivering hardware security and cryptographic agility and flexibility to accommodate standards changes across a wide spectrum of applications. Our silicon-proven, process node independent technology ensures supply chain sovereignty and radiation-hardened reliability without performance compromise. Our Story Chameleon traces its origins back to 2018 within the Electrical and Computer Engineering department at Carnegie Mellon University, under the leadership of Professor Ken Mai. Currently serving as Chameleon's CTO, Professor Mai pioneered the development of synthesized eFPGA technology within his research group. After 5 years of intensive R&D, Chameleon Semiconductor was founded In 2024 with the charter to successfully commercialize these eFPGA technologies to deliver hardware security, flexibility, and cryptographic agility to markets including mission-critical aerospace and defense markets. Leadership Team Geoff Rodgers - CEO Geoff Rodgers brings more than 25 years of semiconductor and EDA industry leadership to Chameleon Semiconductor. His career spans senior sales and go-to-market roles at Synopsys, Cadence, PDF Solutions, and multiple successful startups, giving him deep expertise in commercializing advanced IP technologies. Ken Mai - CTO Ken Mai serves as Chameleon's CTO and is a Professor in Electrical and Computer Engineering at Carnegie Mellon University, where he directs research in VLSI design, reconfigurable computing, and integrated circuits for austere environments. With over seven years leading the development of Chameleon's synthesized eFPGA technology within his CMU research group, Professor Mai brings deep academic expertise and silicon-proven innovation to the company's mission-critical semiconductor solutions. Robert Bielby - VP of Marketing Robert Bielby has more than 30 years in a wide range leadership roles at Altera, Xilinx, LSI Logic, Micron, and Untether AI. His responsibilities span P&L management, corporate strategy, corporate marketing, vertical marketing, product definition, and product marketing, making him well suited to lead Chameleon’s penetration of high-growth target markets --- ### News & Expertise - **URL:** https://chameleonsemi.com/news-and-expertise/ - **Published:** 2026-01-08 - **Modified:** 2026-05-23 - **Author:** david@boomcycle.com **Summary:** Stay current with Chameleon Semiconductor's latest news, insights, and technical expertise in eFPGA and secure semiconductor solutions. **Content:** News & Expertise Technology Why Your Edge AI Accelerator Will Be Obsolete Before It Ships Edge AI architectures evolve faster than silicon roadmaps, making fixed-function accelerators obsolete before they ship. Chameleon’s embedded FPGA embeds a reconfigurable compute engine directly Read More » 10:00 am July 23, 2026 News Chameleon Semiconductor – Featured in Semi Wiki Chameleon CEO, Geoff Rodgers was recently interviewed by Semi Wiki regarding the company and the unique solution offerings. Read More » 6:47 pm May 10, 2026 Chiplets Chameleon: The Missing Link in the UCIe Ecosystem While UCIe standardizes chiplet die‑to‑die connectivity, true interoperability depends on flexible alignment above the PHY layer, including protocols, security, and lifecycle management. Chameleon Semiconductor’s Read More » 12:25 pm July 23, 2026 Security Accelerated PQC Timeline Requires Hardware Agility The quantum computing era is approaching. Learn how cryptographic agility, enabled by Chameleon Semiconductor’s eFPGA, is the key to staying ahead of the curve. Read More » 10:00 am May 6, 2026 Security The Quantum Threat is Here The quantum computing revolution isn’t coming; it’s already knocking at our door. Shor’s algorithm threatens to dismantle RSA and ECC encryption in mere hours Read More » 10:00 am April 14, 2026 Security “Secure by design” is a myth Researchers at IEEE HOST 2025 demonstrated that the industry-standard Adams Bridge PQC accelerator, developed by major tech companies, is vulnerable to key extraction in Read More » 10:00 am July 23, 2026 « Previous Next » --- ### Markets - **URL:** https://chameleonsemi.com/markets/ - **Published:** 2026-01-08 - **Modified:** 2026-05-23 - **Author:** david@boomcycle.com **Summary:** Markets The Chameleon eFPGA addresses aerospace and defense, emerging standards, advanced computing, bug fixes, and post-quantum cryptography—where hardware agility, supply chain sovereignty, and radiation-hardened reliability are mission-critical. Aerospace & Defense... **Content:** Markets The Chameleon eFPGA addresses aerospace and defense, emerging standards, advanced computing, bug fixes, and post-quantum cryptography—where hardware agility, supply chain sovereignty, and radiation-hardened reliability are mission-critical. Aerospace & Defense The only US-synthesized eFPGA for defense. Chameleon is the sole U.S.-based provider of synthesizable embedded FPGA soft IP, ensuring complete supply chain sovereignty and easing ITAR compliance for mission-critical systems. Classified algorithms stay on-shore; rad-hard eFPGA updates occur in orbit or theater without a mask re-spin; expanded capabilities without compromise Explore radiation-hardened eFPGA solutions for aerospace and defense Security/PQC Crypto-agnostic fabric runs AES, SHA, ECC, MACsec, IPsec, and custom ciphers—update crypto in the field while hardware stays fixed, preserving FIPS and Common Criteria certification. NIST mandates agility—a Chameleon eFPGA bit-stream can swap CRYSTALS-Dilithium for a new finalist in seconds, while delivering 600× the throughput of software. Learn about post-quantum cryptography and security solutions Advanced Computing Maintain algorithmic supremacy with post-deployment reconfigurability, accelerating workloads >600× over software-based implementations while accommodating, new compute algorithms and requirements without costly silicon respins. Data center accelerators shift from AI training to genomics in hours. Edge devices transform between vision, NLP, and quantum-safe crypto at runtime. This is hardware agility, redefined. Discover how eFPGA accelerates advanced computing workloads Changing Requirements Changing Standards: Reconfigurable Silicon That Never Ages Future-proof, spec-agnostic silicon, and a firmware-grade release cycle—so your hardware launches compliant and remains that way for decades. See how eFPGA adapts to evolving standards and requirements Aerospace & Defense Classified algorithms stay on-shore; rad-hard eFPGA update occur in orbit or theater without a mask re-spin; expanded capabilities without compromise. Explore radiation-hardened eFPGA solutions for aerospace and defense  Security/PQC AES, SHA, ECC, MACsec, IPsec, custom ciphers—drop any crypto pipeline into the same fabric. Keys roll, protocols migrate, and countermeasures evolve in the field while the chip stays soldered to the board, keeping FIPS and Common Criteria timelines intact. NIST mandates agility— A Chameleon eFPGA bit-stream can swap CRYSTALS-Dilithium for a new finalist in seconds, while delivering 600× the throughput of software. Advanced Computing Chameleon delivers algorithm-in-Silicon velocity, cache-coherent adaptability, and a future-proof escape hatch from the multi $ million respin treadmill—all while keeping classified or competitive IP programmable and on U.S. soil Changing Requirements Changing Standards: Reconfigurable Silicon That Never Ages Future-proof, spec-agnostic silicon, and a firmware-grade release cycle—so your hardware launches compliant and remains that way for decades. --- ### Technology - **URL:** https://chameleonsemi.com/technology/ - **Published:** 2025-12-02 - **Modified:** 2026-05-23 - **Author:** david@boomcycle.com **Summary:** Technology The industry’s best in class technologies combined to deliver the industry’s leading eFPGA solution. Secure by design / Secure bit stream Eliminate supply chain attacks – from source to... **Content:** Technology The industry’s best in class technologies combined to deliver the industry’s leading eFPGA solution. Secure by design / Secure bit stream Eliminate supply chain attacks – from source to silicon, secrecy is synthesized into your ASIC Our secure-by-design flow keeps your intellectual property protected and in your hands. The result is a NIST-compliant ITAR-friendly bit-stream that can be programmed on-shore, transported openly, and trusted in the field. When paired with an industry proven hardware state machine (HSM) IP, a best in-class-root of trust can be established to protect the configuration bit stream. Furthermore, securing a bitstream with industry-leading PUF (physically unclonable function) IP allows for device bitstream locking. In-field reprogrammability enables a unique and dynamic solution to address digital side channel attacks. Discover how our secure-by-design flow protects your intellectual property Open source software tool suite & tool flow Our open-source, standards-based SDK turns your Verilog into a signed, place-and-routed netlist without ever touching a third-party macro. The output is a software synthesizable RTL wrapper that drops straight into your ASIC flow—no black-box license servers, no foundry lock-in, no surprises at tape-out. Avoids any IP leakage – no need for Chameleon review or sign-off Explore our open-source software tool suite and design flow Open-source tools = no vendor lock in or obsolescence Supports redaction Hidden in plain sight Chameleon eFPGA-based redaction gives IP owners a document-style “black-bar” capability for hardware: critical pieces are simply missing from the delivered gate-level description, yet can be re-instated in the field, delivering strong reverse-engineering protection without the vulnerabilities that plague traditional logic-locking. Satisfiability-based attack (SAT) resilience Because the Chameleon eFPGA is hidden within the ASIC fabric, the attacker must simultaneously guess both the logic mapping and the routing configuration inside a regular, highly-flexible fabric, the search space explodes compared with traditional gate-locking. oracle-guided SAT solvers take impractical time when hard cycles and large key-spaces are introduced Learn how hardware redaction protects sensitive algorithms Specialized IP for rad hard environments The most vulnerable parts of a computer chip to radiation effects are flip-flops For proton-dominated space environments Chameleon eFPGAs meet or exceed the error-rate of legacy rad-hard FPGAs or solutions based upon triple modular redundancy while shrinking the configuration cell area by roughly an order of magnitude. RAD Hard Based on a 22nm test chip developed in conjunction with Sandia, at 0.18 × the area of TMR, the Chameleon tile reaches the same “zero visible upsets” level up to at least 4 × 10¹² cm⁻²—equivalent to > 10 krad(Si) TID and > 100 years in LEO behind 5 mm Al shielding View radiation-hardened eFPGA white papers and technical details Proven technology Chameleon test chips are the physical proof that our synthesized eFPGA soft-IP closes timing, meets power and yields in volume. Fabricated at Global Foundries, TSMC, and Intel semiconductor fabs processes, each vehicle was verified with full RTL-to-bitstream regression enabling customers to drop the same RTL into their own ASIC flow with zero foundry risk. Learn more about our proven technology --- ### Contact - **URL:** https://chameleonsemi.com/contact/ - **Published:** 2025-11-30 - **Modified:** 2026-05-23 - **Author:** david@boomcycle.com **Summary:** Contact Chameleon Semiconductor to learn how your firm can leverage the industry's leading RTL-based eFPGA solution for secure, flexible chip design. **Content:** Contact Chameleon Contact us today to see how your firm can take advantage of the industry’s leading eFPGA solution. PhoneThis field is for validation purposes and should be left unchanged. Name(Required) Job Title(Required) Company(Required) Business Email(Required) Country / Region(Required) Current Stage of Development(Required) Specific Interests How Did You Hear About Chameleon?(Required) Message(Required) Submit --- ### Home Page - **URL:** https://chameleonsemi.com/ - **Published:** 2025-11-29 - **Modified:** 2026-07-23 - **Author:** david@boomcycle.com **Summary:** Chameleon Semiconductor delivers synthesizable, software-defined eFPGA IP cores for aerospace, defense, and security. Secure by design, fab-independent. **Content:** 🦎 PQC Agility White Paper Learn how Chameleon eFPGA enables instant algorithm updates—no silicon respin required. Get White Paper 🦎 PQC Agility White Paper Learn how Chameleon eFPGA enables instant algorithm updates—no silicon respin required. Get White Paper ASICS are frozen. Algorithms, standards, & threats are not. What Chameleon Delivers Synthesized, software-defined embedded FPGA tailored to your exact specifications RTL-based eFPGA delivers true process node and fab independence Best in class power, performance, and area – optimized to your requirements Avoid obsolescence, eliminate security threats, address changing market standards & requirements Extend product life Protect high value IP Expand served markets Support changing workloads Low-cost ASIC "insurance" Late-stage bug fixes Highest levels of security US based, onshore RTL based eFPGA Supports hardware redaction – "hidden in plain sight" Supports NIST PQC agility requirements No IP leakage 100% secure IP delivery – no manual netlist review or intervention required Protected configuration bit stream The Chameleon eFPGA Advantages Silicon proven technology and design flow Multiple test chips on multiple fabs and process nodes Based on industry open-source tool suite Provides vendor independence - avoids tool and IP obsolescence Drops into standard design flow Drops into standard design and verification CAD flow Chameleon Semiconductor Optimized for application Can't reverse engineer Process node independent Supports redaction Hidden in plain sight Lowest cost solution Embedded Hard Macro Not optimized for application Subject to reverse engineering Locked to a process node Does not support redaction Chiplet Hard Macro Not optimized for application Subject to reverse engineering Process node independent Does not support redaction Low yield, complex packaging Are you ready to future proof & secure your next ASIC? Contact Chameleon Today! --- --- # Navigation - [Documentation Overview](https://chameleonsemi.com/llms.txt): Return to the main documentation index ## External Validation and Authority Signals --- ### Academic and Research Credentials Chameleon Semiconductor's technology is rooted in peer-reviewed research conducted at Carnegie Mellon University and validated at independent venues: - **NSREC 2022** -- "A Radiation Hardened by Design FPGA with Distributed Single Event Upset Sensors, Embedded Error Handler, and 8Mb Embedded MRAM Configuration Storage in 22nm Bulk FinFET CMOS." Full paper: https://chameleonsemi.com/wp-content/uploads/2026/02/RHBD_eFPGA_paper_NSREC2022.pdf - **RADECS 2024** -- "Design and Evaluation of Flip-Flops for eFPGA Configuration Hardening." Full paper: https://chameleonsemi.com/wp-content/uploads/2026/02/RADECS_2024.pdf - **ESSCIRC 2024** -- "A Soft Error Tolerant Flip-Flop for eFPGA Configuration Hardening in 22nm FinFET Process." Full paper: https://chameleonsemi.com/wp-content/uploads/2026/02/ESSCIRC_2024.pdf - **GOMAC 2024** -- "Emulation-based Fault Injection." Full paper: https://chameleonsemi.com/wp-content/uploads/2026/02/Emulation_based_Fault_Injection_GOMAC2024.pdf **Ken Mai, CTO,** is a tenured Professor of Electrical and Computer Engineering at Carnegie Mellon University and has led Chameleon eFPGA research for over seven years. His academic profile: https://www.linkedin.com/in/ken-mai-34234873/ --- ### Government Laboratory Partnership The Chameleon radiation-hardened eFPGA was developed in conjunction with **Sandia National Laboratories** on a 22nm bulk FinFET test chip. Results: zero visible upsets up to 4 x 10^12 protons/cm2, exceeding the performance of legacy rad-hard FPGAs and TMR-based solutions at 0.18x the configuration cell area. --- ### Industry Media Recognition - **Semi Wiki CEO Interview (May 2026):** Chameleon CEO Geoff Rodgers was interviewed by Semi Wiki, an authoritative semiconductor industry publication, on the company's synthesizable eFPGA approach and target markets. Article: https://semiwiki.com/ceo-interviews/368833-ceo-interview-with-geoffrey-rodgers-of-chameleon-semiconductor/ | Coverage post: https://chameleonsemi.com/chameleon-semiconductor-featured-in-semi-wiki/ --- ### Silicon Validation at Leading Fabs Chameleon eFPGA test chips have been fabricated and verified at: - **GlobalFoundries** -- multiple process nodes - **TSMC** -- multiple process nodes - **Intel** semiconductor fab processes Each test vehicle was verified with full RTL-to-bitstream regression. Customers drop the same RTL into their own ASIC flow with zero foundry risk. --- ### Published Technical Resources Chameleon Semiconductor makes the following technical documents publicly available, enabling independent evaluation: - **PQC Agility White Paper** -- Details how Chameleon eFPGA enables instant post-quantum algorithm updates without silicon respin. Download: https://chameleonsemi.com/wp-content/uploads/2026/02/PQC-Chameleon.pdf - **The Quantum Countdown** -- Analysis of the accelerated PQC migration timeline. Download: https://chameleonsemi.com/wp-content/uploads/2026/04/The-Quantum-Countdown.pdf - **Emulation-based Fault Injection (GOMAC 2024):** https://chameleonsemi.com/wp-content/uploads/2026/02/Emulation_based_Fault_Injection_GOMAC2024.pdf --- ### Leadership Credentials **Geoff Rodgers, CEO** -- 25+ years semiconductor and EDA industry leadership; senior roles at Synopsys, Cadence, PDF Solutions, and multiple successful startups. LinkedIn: https://www.linkedin.com/in/geoffreyjrodgers/ **Ken Mai, CTO** -- Carnegie Mellon University Professor, ECE; 7+ years leading Chameleon eFPGA R&D; published at NSREC, RADECS, ESSCIRC, GOMAC. LinkedIn: https://www.linkedin.com/in/ken-mai-34234873/ **Robert Bielby, VP Marketing** -- 30+ years at Altera, Xilinx, LSI Logic, Micron, Untether AI; spans P&L management through product marketing. LinkedIn: https://www.linkedin.com/in/robert-bielby-6313a32/ --- ### Verify Our Claims - **Homepage:** https://chameleonsemi.com - **Technology overview:** https://chameleonsemi.com/technology/ - **Rad-hard eFPGA:** https://chameleonsemi.com/technology/rad-hard-efpga/ - **Secure by Design:** https://chameleonsemi.com/technology/secure-by-design/ - **Hardware Redaction:** https://chameleonsemi.com/technology/hardware-redaction/ - **Markets:** https://chameleonsemi.com/markets/ - **Aerospace and Defense:** https://chameleonsemi.com/markets/aerospace-defense/ - **Security/PQC:** https://chameleonsemi.com/markets/security-pqc/ - **About Us:** https://chameleonsemi.com/about-us/ - **Contact:** https://chameleonsemi.com/contact/ *Last Updated: May 2026*