# Chameleon Semiconductor -- FAQ / People Also Ask > Answers to the most common questions about embedded FPGA (eFPGA) technology, Chameleon Semiconductor's approach, and how synthesizable eFPGA IP enables hardware security and adaptability for ASICs and SoCs. --- ## What is an embedded FPGA (eFPGA)? An embedded FPGA (eFPGA) is a reconfigurable logic fabric integrated directly inside an ASIC or SoC, rather than existing as a standalone chip on the board. It allows the device to be reprogrammed in the field to change its functionality -- similar to how software updates work for processors -- but at hardware speeds. An eFPGA can implement custom logic, cryptographic engines, signal processing accelerators, or any other digital function, and can be updated after the chip is manufactured and deployed. --- ## What is synthesizable eFPGA soft IP, and how is it different from a hard macro? A **hard macro eFPGA** is a pre-designed, fixed physical block delivered as a black-box layout tied to a specific foundry process node. Customers integrate it as a placed, characterized block -- they cannot change its structure, optimize it for their application, or move it to a different fab without starting over. **Synthesizable eFPGA soft IP** (what Chameleon delivers) is provided as RTL (register-transfer level) source code. It is process-node independent, fab independent, and can be synthesized, placed, and routed in the customer's own ASIC flow alongside their other design blocks. Customers control the PPA optimization. The IP adapts to the target process rather than forcing the design to adapt to the IP. The result: Chameleon eFPGA is optimized for each application, cannot be reverse-engineered, supports hardware redaction, requires no third-party sign-off, and is the lowest-cost solution. --- ## Why would an ASIC designer embed an eFPGA instead of just using a standalone FPGA on the board? A standalone FPGA and an embedded eFPGA serve different purposes. A standalone FPGA sits on the PCB and communicates with the ASIC over interfaces (PCIe, AXI, etc.). An eFPGA is inside the ASIC fabric -- it accesses on-chip memory and logic with zero inter-chip latency and at full SoC speeds. Key advantages of eFPGA over standalone FPGA: - **Performance:** Direct access to on-chip interconnect; no PCIe or external bus overhead - **Security:** No exposed external bitstream loading interface; no external PROM vulnerability - **Power:** No off-chip I/O power consumption; lower system power - **Cost:** One chip replaces what would otherwise require an ASIC plus a discrete FPGA - **IP protection:** Hardware redaction capability is impossible with an external FPGA - **ITAR compliance:** Classified algorithms stay inside the SoC; no external configuration device to intercept --- ## How does Chameleon protect the eFPGA bitstream from interception or reverse engineering? Chameleon uses a multi-layer approach: 1. **Embedded loading:** The bitstream is loaded internally within the SoC -- there is no external PROM or configuration bus that an attacker can probe. 2. **Encryption:** The bitstream can be encrypted using industry-standard algorithms. 3. **Hardware root of trust:** Paired with a hardware state machine (HSM) IP, the eFPGA establishes a hardware root of trust that authenticates the bitstream before loading. 4. **Device locking with PUF:** Integrating a physically unclonable function (PUF) locks the bitstream to a specific device. Even if the bitstream file is obtained, it cannot run on any other chip. 5. **Hardware redaction:** Critical logic blocks are simply absent from the gate-level netlist. There is nothing for an attacker to find at the netlist level. 6. **In-field reprogrammability:** If a side-channel attack vector is discovered post-deployment, the eFPGA configuration can be updated in the field to close the vulnerability without a hardware respin. --- ## What is hardware redaction, and why does it matter? Hardware redaction is a technique where critical IP blocks are mapped into the Chameleon eFPGA fabric rather than implemented as visible gates in the ASIC netlist. The gate-level description delivered to a foundry, a supply-chain partner, or an end customer is missing those blocks entirely. They can be re-instantiated in the field via an authenticated, encrypted bitstream. This gives IP owners a "black-bar" capability analogous to redacting sensitive text in a classified document -- except the redacted content is hardware logic. No attacker with access to the chip layout or a reverse-engineered netlist can see the classified algorithm because it is not present in any exposed form. Hardware redaction also defeats satisfiability-based (SAT) reverse-engineering attacks. Because the attacker must simultaneously guess both the logic mapping and the routing configuration inside a flexible eFPGA fabric, the search space is exponentially larger than traditional gate-locking approaches. Oracle-guided SAT solvers take impractical time against Chameleon's hard-cycle and large-key-space structure. --- ## What is post-quantum cryptography (PQC) agility, and why does hardware need it? Post-quantum cryptography refers to cryptographic algorithms designed to resist attacks from quantum computers. Current widely-deployed algorithms (RSA, ECC) are vulnerable to Shor's algorithm on a sufficiently powerful quantum computer. NIST has standardized a set of PQC algorithms (including CRYSTALS-Dilithium and CRYSTALS-Kyber) and mandates that government and critical infrastructure systems migrate to them. **Hardware agility** is the ability to update which cryptographic algorithm the hardware implements -- in the field, after deployment -- without redesigning or re-spinning the chip. This matters because: - NIST and NSA timelines are accelerating (Google set a 2029 target, two years ahead of the NSA 2031 goal) - New PQC finalists may emerge; existing standards may be revised - Hardware designed today will be deployed for 10-20 years; it must remain cryptographically sovereign throughout Chameleon eFPGA enables PQC agility by hosting the cryptographic pipeline in reconfigurable fabric. A bitstream update swaps one PQC algorithm for another in seconds, while the chip stays soldered to the board and FIPS/Common Criteria certifications remain intact. Chameleon's eFPGA delivers 600x the throughput of software-based PQC implementations. --- ## Is Chameleon eFPGA ITAR compliant? Chameleon Semiconductor is the only U.S.-based provider of synthesizable eFPGA soft IP. Our design, development, and IP delivery operations are fully onshore. The resulting bitstream is ITAR-friendly: classified algorithms can be developed, loaded, and managed on U.S. soil without requiring access by foreign nationals or foreign foundries. Because our eFPGA IP is process-node independent, defense customers are not forced to use a foreign foundry to access eFPGA capability. The IP can be synthesized at any U.S.-accessible fab. This eliminates the ITAR compliance friction that foreign-sourced eFPGA solutions create for prime contractors and DoD program offices. --- ## What radiation environments is Chameleon's rad-hard eFPGA suited for? Our radiation-hardened eFPGA IP has been validated for: - **Low Earth orbit (LEO):** Greater than 100 years survivability behind 5 mm aluminum shielding - **Proton-dominated environments:** Zero visible upsets up to 4 x 10^12 protons/cm2 - **Total ionizing dose:** Greater than 10 krad(Si) TID - **Nuclear-hardened ground systems:** Tested and characterized at Sandia National Laboratories The underlying patented DSM (distributed single-event upset mitigation) flip-flop technology achieves 3,735x critical-section reduction compared to standard designs, at only 0.18x the area of triple modular redundancy (TMR). It outperforms both TMR and DICE (dual interlocked cell) approaches in error-rate and area efficiency. Applications include LEO and GEO satellites, deep space probes, nuclear-hardened ground stations, and airborne defense systems that require in-orbit or in-field reconfiguration without mask respins. --- ## Can the eFPGA be updated in orbit or in the field after deployment? Yes. In-field and in-orbit reconfigurability is a primary design objective for Chameleon rad-hard eFPGA. Updates are delivered as authenticated bitstreams over whatever communication channel the host system provides (uplink, secure network, physical interface). The eFPGA can receive a new bitstream, authenticate it, and reconfigure without any hardware changes. This eliminates the need for a mask respin -- which costs millions of dollars and takes 18-24 months -- whenever an algorithm update, standards change, or security patch is required. --- ## How does Chameleon compare to a chiplet-based eFPGA? A chiplet-based eFPGA is a separate die that connects to the host SoC through a die-to-die interface (such as UCIe). It is process-node independent (like Chameleon) but shares several disadvantages compared to our synthesizable approach: - It is not optimized for the target application (generic fabric) - It is subject to reverse engineering (physical die accessible to adversaries) - It does not support hardware redaction (the full fabric is present and observable) - It introduces yield risk from the chiplet itself and complex packaging overhead - It requires a PHY-layer interface that consumes die area and power Chameleon eFPGA avoids all of these. It is embedded within the host ASIC fabric, invisible to physical inspection, optimized to the application, and adds no inter-die interface overhead. --- ## What fabs and process nodes has Chameleon eFPGA been validated on? Chameleon test chips have been fabricated and verified at: - **GlobalFoundries** -- multiple process nodes - **TSMC** -- multiple process nodes - **Intel** semiconductor fab processes Each vehicle was verified with full RTL-to-bitstream regression. Customers drop the same RTL into their own ASIC flow at any of these fabs with zero foundry risk. Because the IP is synthesizable RTL, it can also be targeted at process nodes not yet characterized -- the tool flow handles adaptation. *Last Updated: May 2026*